The development of electronic data processing systems, including microprocessor systems, has resulted in various techniques for storing the instructions that the computer uses in carrying out its intended operations and in fetching the instructions from memory as they are needed during the operation of the data processing system. The systems commonly employ processing implementations whereby the instructions are fetched sequentially from memory one at a time, as they are required for processor operation. Typically, as each instruction is fetched from memory, it is stored in an instruction register, the contents of which are decoded to cause the computer to execute a particular data processing operation, and another register, commonly referred to as a program counter or location counter, has its contents updated, to identify the memory address of the next instruction to be executed by the processor. Then, upon completion of the execution of the present instruction, the next instruction identified by the location counter is fetched from memory and stored in the instruction register, as the cycle is repeated for each respective instruction.
In an effort to reduce processor operating time, lookahead or pre-fetching schemes have been developed, whereby the system begins fetching a new instruction from memory once it has begun executing the present instruction, the contents of the present instruction contained in the instruction register having been decoded, thereby permitting system operation to proceed.
Now, along with the development of processor instruction execution and pre-fetching schemes, improvements in information storage systems have enabled an increasingly greater memory capacity to be utilized by the processor. With the advance of memory packaging schemes, such as improved LSI techniques, very large portions of memory space have been able to be implemented in modular form, so that effectively as much actual memory space as is necessary for any system operation can be provided simply by configuring the memory to contain the appropriate number of memory modules. In other words, information storage is implemented through a bank of memory modules, each of which may be considerable storage capacity in itself, thereby achieving an extremely large system storage capability.
Since each memory module is typically configured identically to every other module in the bank, a selective addressing scheme is required to properly identify the particular module in the bank that contains information to be retrieved, such as instructions or data, or into which information is to be written. The scheme chosen must have the capability of being adaptive, since there may occur situations where an instruction being executed references data that is located in a memory module other than the memory module from which the instruction being executed is obtained. For the purposes of selecting the proper memory module, additional address registers, that may be considered to be extensions of the internal address registers of the system, may be provided for identifying the appropriate memory module that contains the addressed memory location of interest. These registers have conventionally been controlled by softwave via special instructions, which has undesirably resulted in an increase in processor complexity (from both a software and microcode standpoint) and execution time.